Linear feedback shift-register (LFSR) circuits have long been known to create random test data for complex very large scale integrated (VLSI) circuits containing many thousands of interconnected circuits, most of which are inaccessible for testing purposes. Because of the complexity of the internal interconnections and their interdependencies, detecting the presence of defective elements is difficult and time consuming.
By way of example, a semiconductor chip with fifty input terminals would require a total of 2.sup.50 binary input combinations. Applying such a large number of inputs patterns during testing, followed by reading the corresponding output responses and, finally, comparing these responses with expected values obtained from simulation is an impossible task.
Giedd et al, in U.S. Pat. No. 3,614,608 describes a random number generator used for automatically generating test vectors. This generator considerably reduces the number of test patterns required to test a circuit. This reduction is possible because a random pattern generator, unlike a binary test generator, produces a succession of binary words, wherein the split between "0"s and "1"s approaches 50% for a substantial number of successive words. Each input to the device under test has a 50% chance of receiving a "0" or a "1" with far fewer number of input patterns.
Pure random pattern generators have been modified over the years to reduce test time. A technique designed to introduce a certain degree of intelligence to test pattern generation is described in U.S. Pat. No. 3,719,885 to R. G. Carpenter et al. This method, known as Weighted Random Pattern (WRP) generation, consists of creating a statistically predetermined greater number of "0"s or "1"s which are then applied to the Device Under Test (DUT). These WRP are far more efficient in accessing internal circuit elements within the DUT than flat random patterns.
A further improvement over Giedd and Carpenter is described in U.S. Pat. No. 4,801,870 to E. B. Eichelberger et al. A method and apparatus for testing VLSI circuits and more particularly, a Level Sensitive Scan Design (LSSD) is described, in which differently configured sequences of random patterns are applied in parallel to each input terminal of the DUT. Output responses are then collected from each output in parallel and combined so as to obtain a signature function of all of the sequences of parallel outputs. Ultimately, the test signature is compared with a known good "signature" obtained by computer simulation. This use of "signatures" in lieu of comparing each individual test response with a known good output response is taught by Gordon et al in U.S. Pat. No. 3,976,864.
Several variations of signature analyzers have been described. By way of example, Th. Sridhar discloses in U.S. Pat. No. 4,601,034 a configurable parallel signature analyzer used for testing high density VLSI memory elements. In another version, fully described in the IBM Technical Disclosure Bulletin, Vol. 29, No. 1, June 1986, W. K. Chui shows a High Speed Parallel Signature Board that converts eight different digital data streams into eight independent 16-bit signatures simultaneously. In yet another variation of a signature analyzer, B. P. Fenton et al show in the IBM Technical Disclosure Bulletin, Vol. 26, No. 12, May 1986, how to obtain multiple line signature analysis by using parallel LFSRs to test logic circuit at functional speeds.
LFSRs have also produced signatures at the outputs of a DUT to represent current states in dependence upon prior states and received response signals. This is achieved by allowing checking to occur during testing in contrast to conventional signature analysis, wherein comparison only occurs at the end of a testing sequence. Such apparatus is disclosed by M. Whelan in U.S. Pat. No. 4,601,033.
Classic LFSRs, as those described in the cited references, are sequential. Binary values are shifted from one shift-register stage to the next by a clock until they eventually exit via an LFSR output. It is well known that sequential operations are slow in nature and must therefore be compensated by running the LFSR at high speeds to achieve the necessary data generation and compression rates which are the norm of WRP generators. For high end systems, high speed data generation and compression can only be achieved by high performance circuits and a high speed clock. High speed circuits also require more power and extra cooling, both of which take up considerably more space in the system than that needed in an implementation with low performance circuitry such as CMOS, instead of bipolar technology.